Design of an Integrated Circuit (IC) chip such as Application-Specific ICs (ASICs) and system-on-chips (SoC's) is a very complex, expensive, and time-consuming task. To help streamline this task, designers often utilize silicon IPs (also known as intellectual property blocks, IP cores, or integrated circuit macros) to facilitate the design task. IPs are units of reusable design whose use may have been licensed from a third party IP vendor. IPs may represent design components such as processor units, interface protocols, data storage elements, functions, etc. that may be utilized in the design of an ASIC or SoC. IPs commonly take the form of a digital, analog, or mixed signal IC described in a hardware description language (HDL) such as Verilog, VHDL, or System C but may also be represented as a netlist or physical layout. While using IP blocks in a design can provide significant efficiencies when compared with designing a chip at the transistor level or gate level, management of a large number of IP blocks from multiple IP vendors in various design languages and databook format and configurations has its own complexities.
As ASICs, SoCs and other designs grow larger and more sophisticated, the task of integrating complex silicon IP blocks into a system becomes increasingly labor intensive and time consuming. Additionally, the number and complexity of IPs used in SoCs and ASICs is also increasing as designers are more and more frequently taking advantage of IPs for SoC or ASIC designs. While an average design in the year 2000 might have had less than 20 IPs, the average number of IPs increased to almost 100 per design in the year 2003 and is expected to increase to 500 or more in the year 2006. The percentage of total IC area taken by IP designs is also increasing due to the increasing complexity of IP designs. The difficulty in integrating IPs is exacerbated by the fact that for most designs the majority of the IPs are developed by third party IP developers. The use of third party IPs complicates the task of integration of these IPs into the design because of concern about maintaining confidentiality of information and protecting intellectual property rights and because of different design styles and ad hoc verification of non-standard databooks and delivery packages, often resulting in a failure of third party IPs to meet internal requirements. This often results in additional resources being required to evaluate and validate third party IPs and, in many cases, in-house designers must spend more time verifying an IP than it took to develop in the first place.
Accordingly, SoC and ASIC designers desire to bring in an external or third party IP, assess the IP for compliance with their organization's standards, requirements, and needs, and then integrate the IP into the in-house design flow for further evaluation or analysis before buying or committing to the IP. This process, however, is currently error-prone and ad hoc as SoC and ASIC designers must manually evaluate each IP for compliance with rules, tools, or other organizational requirements, a time-consuming and expensive process. An IP may be required to satisfy both organization standards and industry standards. Industry standards, such as PCI Express, USB On-the-Go, or 10-Gbit/second Ethernet, are well-known and allow IP developers to adapt their IPs to meet these standards. Many of the organization's own standards, however, must be kept confidential and proprietary, making it difficult for third party IP developers to ensure that their IPs conform to the organization's requirements. An organization often desires to keep its internal design and fabrication processes confidential because, among other reasons, publishing requirements for IPs may give competitors insight into upcoming, next-generation products and fabrication capabilities. The resources required to assess and integrate third party IPs, when combined with the dramatic increase in the use of IPs, result in a need to reduce the time and other resources currently used to manually assess and integrate IPs. There is, therefore, a need for an effective and efficient system to assess and integrate silicon IPs into in-house design flows efficiently, cost-effectively, and in a timely and consistent manner.